The main HBM suppliers for AI accelerators are SK hynix, Samsung and Micron, the three memory makers racing to ship high-bandwidth memory for GPUs and custom AI chips. As of October 2026 all three say they are shipping HBM4 in volume, and SK hynix and Samsung both say they have sent HBM4E samples to customers. The race is about who ships each generation first, at what speed per pin, and in what stack heights, and each company describes its position in its own releases.
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What HBM is and why accelerators need it
High-bandwidth memory stacks several DRAM dies vertically on a base die and connects the stack to the processor through a very wide interface on the same package. The width is the point: an HBM4 stack moves data over 2,048 bits at once, which is what lets a GPU or custom accelerator feed its compute units fast enough for large AI models. How HBM differs from DDR and GDDR memory is covered in our HBM memory explainer.
JEDEC, the standards body, published the HBM4 standard (JESD270-4) on April 16, 2025. Its baseline:
| JEDEC HBM4 parameter | Value |
|---|---|
| Interface width | 2,048 bits |
| Transfer speed | Up to 8 Gb/s |
| Bandwidth per stack | Up to 2 TB/s |
| Independent channels | 32 per stack (double HBM3’s 16) |
| Stack heights | 4-, 8-, 12- and 16-high |
| Maximum capacity | 64 GB (32 Gb dies, 16-high) |
All three suppliers now quote pin speeds above JEDEC’s 8 Gb/s, which is why their per-stack bandwidth figures exceed 2 TB/s.
Where each supplier stands
| Company | Latest HBM product | Status as the company states it | Date of statement |
|---|---|---|---|
| SK hynix | HBM4 | “Began mass shipments of HBM4 in the second quarter,” ramping in the second half of 2026 | Jul 29, 2026 |
| SK hynix | HBM4E | Sample shipments completed in the first half of 2026 | Jul 29, 2026 |
| Samsung | HBM4 | Mass production and commercial shipments, 11.7 Gb/s | Feb 12, 2026 |
| Samsung | HBM4E | “Industry’s first HBM4E samples” shipped to major customers | Jul 30, 2026 |
| Micron | HBM4 36GB 12-high | Volume shipments began in calendar Q1 2026 | Mar 16, 2026 |
| Micron | HBM4 48GB 16-high | Samples shipped to customers | Mar 16, 2026 |
The “first” claims overlap, and each is the company’s own: Samsung calls its February 2026 HBM4 shipment “industry-first,” SK hynix called its September 2025 announcement the world’s first completed HBM4 development, and both report HBM4E sampling in 2026.
SK hynix
SK hynix said on September 12, 2025 that it had completed HBM4 development and prepared mass production. It gave these figures: 2,048 I/O terminals, double the previous generation; bandwidth doubled; power efficiency improved by more than 40%; and an operating speed of over 10 Gb/s, above the JEDEC standard. The company makes the stacks with its Advanced MR-MUF process and its 1b-nanometer (fifth-generation 10-nanometer-class) DRAM.
In its second-quarter 2026 results on July 29, 2026, SK hynix reported revenue of 79.3187 trillion won and said it “began mass shipments of HBM4 in the second quarter and will ramp up production in the second half of the year.” It said HBM4 achieved “customer-required operating speeds” and that HBM4E “completed sample shipments in the first half.”
Samsung
Samsung announced on February 12, 2026 that it had started mass production of HBM4 and shipped it commercially. Its stated specifications:
- transfer speed of 11.7 Gb/s, with headroom to 13 Gb/s;
- up to 3.3 TB/s of bandwidth per stack, which Samsung says is 2.7 times HBM3E;
- 12-high stacks of 24 GB to 36 GB, with 16-high stacks planned to reach 48 GB;
- its sixth-generation 10-nanometer-class (1c) DRAM on a 4-nanometer logic base die.
At the time Samsung expected HBM4E sampling in the second half of 2026 and custom HBM samples in 2027. Its second-quarter results on July 30, 2026 reported that the memory business “scaled up HBM4 sales” and shipped “the industry’s first HBM4E samples to major customers.” Samsung’s foundry business also benefits, citing “HBM base-die demand,” since Samsung makes HBM4 base dies on its own 4-nanometer process.
Micron
Micron said on March 16, 2026 that it had begun volume shipments of HBM4 36GB 12-high in the first calendar quarter of 2026, designed for Nvidia’s Vera Rubin platform. Micron’s figures: pin speeds over 11 Gb/s, more than 2.8 TB/s of bandwidth per stack, and more than 20% better power efficiency than its HBM3E. It also shipped samples of a 48GB 16-high HBM4 stack, 33% more capacity than the 12-high part.
Micron reported fiscal 2026 results on September 30, 2026, with fourth-quarter revenue of $54.23 billion and full-year revenue of $133.19 billion.
Side by side: the HBM4 numbers each company publishes
| Spec | SK hynix HBM4 | Samsung HBM4 | Micron HBM4 |
|---|---|---|---|
| Pin speed | Over 10 Gb/s | 11.7 Gb/s (up to 13 Gb/s) | Over 11 Gb/s |
| Bandwidth per stack | Double the previous generation | Up to 3.3 TB/s | More than 2.8 TB/s |
| Volume shipments began | Q2 2026 | February 2026 | Calendar Q1 2026 |
SK hynix measures its gains against its previous generation and Micron against its own HBM3E, so the companies’ improvement claims are not directly comparable; SK hynix states power efficiency up more than 40%, Micron more than 20%.
Why HBM supply shapes the accelerator market
Data-center accelerators in the AI chips catalog, such as Nvidia’s GPUs and Broadcom-built XPUs, carry HBM stacks packaged next to their compute dies; Broadcom’s 3.5D platform alone takes up to 12 stacks per package. An accelerator cannot ship without its memory, so HBM output sets a limit on accelerator output. HBM is also an export-controlled item in its own right: since December 2024, U.S. rules list HBM stacks above a memory bandwidth density of 2 GB/s per mm² under ECCN 3A090.c; the wider rules are in our AI chip export controls explainer. Profiles of the three memory makers are in the AI companies directory.
