TSMC matters for AI chips because it both manufactures the leading-edge silicon and packages it: Nvidia, Broadcom’s custom XPUs and Intel’s Gaudi 3 are all built on TSMC processes by their makers’ own account, and TSMC’s CoWoS packaging is what Broadcom’s largest XPUs use to place compute dies next to HBM memory. As of its July 2026 results, 3-nanometer and 5-nanometer chips made up 63% of TSMC’s wafer revenue. Not every AI chip uses TSMC, though; Huawei, for one, says it designs for the process nodes available in mainland China.
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Two jobs: wafers and packaging
A modern AI accelerator is made in two stages. First the compute dies are fabricated on an advanced logic process. Then those dies are mounted, together with stacks of high-bandwidth memory, on an interposer that carries thousands of short, fast connections between them. TSMC does both.
The vendors say so on their own pages:
| Chip | Vendor’s statement on TSMC |
|---|---|
| Nvidia Blackwell GPUs | 208 billion transistors, “manufactured using a custom-built TSMC 4NP process”; two reticle-limited dies linked at 10 TB/s |
| Broadcom 3.5D XPU | Lead design uses “TSMC’s cutting-edge process nodes and 2.5D CoWoS packaging technologies” |
| Intel Gaudi 3 | “Manufactured in TSMC 5nm process,” two compute dies |
Specifications for these and other accelerators are collected in the AI chips catalog.
Advanced nodes: N3, N2 and what comes next
TSMC says it was the first foundry to move 3-nanometer FinFET (N3) technology into high-volume production, in 2022, and describes N3 as a full-node advance over 5 nm. It followed with N3E and N3P “for better power, performance, and density.”
The next step changes the transistor. TSMC’s 2-nanometer (N2) process “started volume production in 4Q25 as planned” and uses the company’s first-generation nanosheet transistors, a gate-all-around design that replaces FinFETs. An enhanced N2P is scheduled for volume production in the second half of 2026. After that, TSMC’s A16 combines nanosheet transistors with a backside power rail, which moves power delivery to the back of the wafer.
Further out, TSMC and ASML announced in September 2026 a joint move from 6-inch to 12-inch photomasks for High NA EUV lithography, which they say should “increase fab productivity, lower chipmaking costs and remove stitching constraints.” The plan targets a 12-inch mask pilot line in 2031, and TSMC said it plans to use High NA in high-volume manufacturing from 2030. Stitching is relevant to AI chips in particular, because the largest accelerators are already as big as a single exposure allows.
AI customers are already naming these nodes. Meta and Broadcom described one of the MTIA chips in their April 2026 partnership as “the industry’s first 2nm AI compute accelerator,” and Fujitsu said its FUJITSU-MONAKA processor, packaged with Broadcom’s 3.5D technology, is a 2-nanometer design.
CoWoS: the packaging step
CoWoS (Chip on Wafer on Substrate) is TSMC’s 2.5D packaging family. TSMC calls it “the essential foundation for high-performance computing (HPC) and artificial intelligence (AI) products.” There are three variants:
| Variant | Interposer | In production since | Size TSMC states |
|---|---|---|---|
| CoWoS-S | Silicon interposer with deep trench capacitors | 2012 | Up to 3.3x reticle (about 2,700 mm²) |
| CoWoS-R | Redistribution-layer (RDL) interposer, polymer-based | 2023 | 4 μm minimum pitch |
| CoWoS-L | RDL interposer with embedded local silicon interconnect (LSI) | 2024 | 3.5x reticle |
The reticle is the largest area a lithography tool can expose in one shot, so an interposer several times that size lets a vendor place two large compute dies and many HBM stacks in one package. Nvidia’s Blackwell GPUs, for example, combine two reticle-limited dies in one package, and Broadcom’s 3.5D platform integrates more than 6,000 mm² of silicon with up to 12 HBM stacks.
What the Q2 2026 results show
TSMC reported its second quarter of 2026 on July 16, 2026. Its node mix shows where demand sits.
| Q2 2026 metric | Figure |
|---|---|
| Revenue | NT$1,270.38 billion (US$40.20 billion) |
| Gross margin | 67.7% |
| 2 nm share of wafer revenue | 3% |
| 3 nm share of wafer revenue | 30% |
| 5 nm share of wafer revenue | 33% |
| 7 nm share of wafer revenue | 11% |
| 7 nm and below, combined | 77% |
| Q3 2026 revenue guidance | US$44.6–45.8 billion |
Read against TSMC’s node timeline, the table shows the two most advanced FinFET generations, 3 nm and 5 nm, carrying almost two-thirds of wafer revenue, while N2 contributed 3% in its third quarter of volume production. Looking ahead, TSMC said it expects third-quarter business “to be supported by continued strong demand for our leading-edge process technologies, including the steep ramp-up of our 2-nanometer technology.”
TSMC Arizona
TSMC’s U.S. manufacturing site is in Arizona. As of October 2026, TSMC’s Arizona page says its planned investment there has grown from $12 billion to $265 billion and covers six logic fabs, two advanced packaging facilities and an R&D center. By TSMC’s account:
- the first fab began high-volume production on N4 in the fourth quarter of 2024;
- the second fab is planned for N3;
- the third fab is planned for N2 and A16;
- construction of the first advanced packaging fab began in early 2026.
The packaging plants matter for AI in particular, because they would put advanced packaging, not only wafer fabrication, in the U.S.
Who does not run through TSMC
The shorthand that every AI chip runs through TSMC has exceptions. Huawei said at Huawei Connect 2025 that it builds its Ascend systems “with the semiconductor manufacturing process nodes that are practically available to the Chinese mainland,” and U.S. rules restrict which advanced chips and tools can reach Chinese companies. The memory side is also separate: HBM stacks come from memory makers such as SK hynix, Samsung and Micron, not from TSMC. TSMC’s role is the leading-edge logic and the package that joins logic and memory together; company profiles for the chipmakers involved are in the AI companies directory.
